This invention is generally directed to improvements in semiconductor memories. It is particularly directed to an improved I/O (Input/Output) scheme for semiconductor memories such as static RAMs (Random Access Memories).
Typical I/O schemes for static RAMs of the type considered herein frequently include a plurality of predata lines which couple data from a main data bus to a plurality of memory cells. Externally derived data is applied to the main data bus via a data bus driver.
Generally, the main data bus and the predata lines include D.C. load transistors which are held on during read and write operations. In a 16K by 1 static RAM, these load transistors consume power, but not at a level which is critical.
In wide word memories such as 4K by 4 static RAMs, the I/O scheme may include four times as many predata lines and main data buses. Hence, four times as many D.C. load transistors are required, and the power consumed increases by a factor of four. Consequently, the typical I/O scheme for a narrow word memory has not been directly convertible to a corresponding scheme for a wide word memory using conventional techniques without paying a penalty in terms of power consumption.